3-D VLSI Architecture Implementation for Data Fusion Problems Using Neural Networks

This paper gives an overview of hardware implementation techniques employed in solving real-time classEfication problems using Neural Network, Principle Component Analysis (PCA), and Independent Component Analysis (ICA) techniques. The first part of the paper reviews digital, analog, and hybrid strategies for hardware implementation, outlining their advantages and disadvantages. The second part focuses on dedicated VLSI chips developed at the Jet Propulsion Laboratory (JPL). A flexible neural network chip with 64 neurons and a 64x64 synaptic weight array with 8-bit resolution is first presented. This chip can be theoretically cascaded to form a larger network, connected in parallel to improve a)tnamic range or resolution, or connected in a loop to create a feedback neural network. A second neural network chip is presented that was fabricated using Silicon-On-Insulator (Sol) technology. This second chip operates at 1.5V, has neurons with variable transfer functions, and has completely compatible inputs and outputs, allowing simple and direct cascading and feedback. A 64x64 synaptic weight array chip is then introduced that has 8-bit resolution and a time response of less than 250ns. This chip was stacked to obtain a cube of 64 chips with an estimated data processing speed of I O i 2 operations per second. A data input chip called the Column Loading Input Chip (CLIC) was designed, fabricated in l . 0 p CMOS technology, and tested. The chip can take 64x64 digital bytes and convert them into 64x64 analog inputs to a 3-0 parallel processing cube. The CLIC was designed to raster through a large image window, taking a new 64-byte column or row of data from the main image every 250ns. The cube processes this data using PCA or ICA techniques and passes its output to a neural network classlJier. In the cube architecture, power consumption is one of the most important concerns and has, so far, inhibited designs of larger arrays. However, recent,SOI technology seems capable of improving major aspects of performance by providing power consumption reduction, latch-up avoidance, and mixed signal noise reduction. A new 3-0 architecture is proposed which is similar to the original cube but is more robust for stacking and easier to test, and its application to a hyperspectral sub-pixel classijkation problem is discussed.